1. Field of the Invention
This invention relates to the formation of a gradient doped profile region for an integrated circuit structure. More particularly, this invention relates to the formation of a gradient doped profile region of an integrated circuit structure between a heavily doped source/drain region and a channel region of an MOS device using a high dose drain implant and a retrograde gate electrode as a mask.
2. Description of the Related Art
In the construction of an MOS device in an integrated circuit structure formed in a semiconductor substrate, high strength electric fields are created or generated at the interface or junction between the heavily doped drain region and the channel region in the substrate beneath the gate electrode. Such high strength electric fields, in turn, cause the formation of hot carriers which are directed toward the gate electrode and the underlying gate oxide, resulting in damage to the fragile gate oxide which is very thin, i.e., only about 40-100 Angstroms thick.
This problem is very well known and has resulted in the widely practiced remedy of forming a lightly doped drain (LDD) region between the heavily doped drain region and the channel region in the semiconductor substrate. This LDD region provides a transition between the heavily doped drain region and the channel region to thereby lower the strength of the electric field generated adjacent the channel region and the gate oxide thereon, which, in turn, lowers the flux of hot carriers generated by the electric field.
This prior art approach of forming LDD regions is illustrated in FIG. 1 wherein a semiconductor substrate 2 is shown having a gate electrode 4 formed over a gate oxide 6 on the surface of substrate 2 with field oxide isolation portions 8 formed in the substrate laterally spaced from gate electrode 4 to allow source/drain regions to be formed in substrate 2 between gate electrode 4 and field oxide isolation 8. Before implanting substrate 2 to form the source/drain regions, the substrate is blanket implanted to lightly dope substrate 2, for example, with boron at a dosage of about 5.times.10.sup.13 boron atoms/cm.sup.2 to provide a P-region in an N well of a semiconductor substrate; or with arsenic (or phosphorus) at a dosage of about 5.times.10.sup.13 atoms of arsenic/cm.sup.2 (or 2.times.10.sup.14 atoms of arsenic/cm.sup.2) to provide an N-region in a P doped semiconductor substrate or a P well in a semiconductor substrate. This doping step then forms conventionally doped LDD regions 10 and 12 in the substrate, respectively, on either side of channel region 18 formed in substrate 2 beneath gate electrode 4 and gate oxide 6. A layer of oxide is then deposited over the entire structure and the oxide layer is then anisotropically etched, resulting in the formation of oxide spacers 20 on the sidewalls of gate electrode 4 which cover LDD portions 10 and 12 of the lightly-doped substrate immediately adjacent channel region 18. A conventional source/drain implant of the exposed portions of substrate 2 in between oxide spacers 20 and field oxide isolation 8 is then carried out resulting in the formation of conventional heavily doped (N+ or P+) source/drain regions 14 and 16. However, source/drain regions 14 and 16 are respectively separated from channel region 18 beneath gate electrode 4 by lightly doped LDD regions 10 and 12, which effectively solves the hot carrier problem and resulting degeneration of gate oxide 6.
However, it will be seen that the current flow passing between the source/drain region 14 and source/drain region 16 through channel 18 must also pass through LDD regions 10 and 12. Since LDD regions 10 and 12 constitute lightly doped regions of the semiconductor substrate, the resistance of these LDD regions is higher (because the lighter dopant level of the LDD regions results in the semiconductor substrate being a poorer electrical conductor through these regions). Such higher resistance introduced in the current path between the source and drain regions degrades the performance of the resulting MOS device, particularly at low voltages, e.g., voltages of as low as 2-3 volts. Since the use of lower voltages has become of particular importance for integrated circuit devices used in portable computers, such degraded performance of the LDD-containing MOS transistor at low voltage is generally becoming unacceptable.
It would, therefore, be desirable if the problems of high strength field generation and resultant hot carrier generation adjacent the junction between the channel region and the heavily doped drain region in the substrate could be solved without creating the conventional high resistance LDD region therebetween.